This disclosure relates to a broadcast bus of an integrated circuit that can broadcast an addressed message to addressed logic blocks of the integrated circuit.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Modern electronic devices, such as computers, mobile phones, digital cameras, and media players, use integrated circuits to operate on data. Many integrated circuits, including many field programmable gate array (FPGA) integrated circuits, use control and status registers to store operating modes, filtering coefficients, control settings, and so forth. There may be thousands of control and status registers in some integrated circuits. Moreover, these registers may hold data between 18-32 bits wide in some cases. In a programmable device such as an FPGA, soft logic programmed into the fabric of the FPGA may enable a host integrated circuit to update and/or request statuses from the control and status registers of the FPGA. Indeed, the soft logic programmed into the FPGA may consume a significant portion (e.g., 20% or more) of the FPGA fabric, using networks of address decoders and multiplexers to convey signals to and from the control and status registers of the FPGA. These soft logic address decoders and multiplexers may also offer relatively slow and/or inefficient performance.